BigClock
From NortHACKton
Nottinghack gave us one of their Big Clocks.
Leeds Hackspace have one too and have collected some datasheets.
Contents |
Construction
The clock consists of a case containing a power/signal distribution board and two clock modules. A radiocode receiver is mounted externally. The distribution board accepts mains power, a connection to the radiocode receiver, and connections to each of the clock modules (one faces each way). It also has some RJ45 connectors which are marked RS485. Ribbon cables and mains power cables connect it to the clock modules.
Radio code receiver
The radiocode receiver is a dumb device that provides only a tuned, sliced version of the radiocode data: a digital signal rather than RF, but with no format conversion. This might be for either MSF or DCF77 signals, though MSF is probably more likely.
Power Supply
Mains power from the common connector board is fed to a power supply unit in each clock module. This provides DC power to the controller board and supplies to a pair of fluorescent tubes (backlighting for the LCD) switched by I/O on the controller board.
Clock controller
Inside each clock casing is a controller which accepts the radiocode signal and perhaps an RS485 connection. It has 2 17C756A PICs and a daughterboard holding a NEC V25 micro, some EPROM and RAM. It is marked INFOTEC BCC3 BRUNEL CLOCK CONTROLLER.
Controller
The controller motherboard contains 2 PICs, which appear to be linked to the daughterboard with 4 HC574 latches and an HC245 buffer. Between the PICs and the LCD buffer cable are a voltage regulator and 3 high-current opamps. Possibly providing the bias voltages.
On the controller, near the connection to PSU and I/O, there are 2 6N137 optocouplers (arranged in a way that suggests one operates in each direction - these may connect to the radiocode reciever, which appears to be optoisolated from the CPU power), and 2 MAX483 bidirectional 2-wire RS485 drivers. LK3 near the drivers is unpopulated. There is also an unused connector marked COM0 and an ST232C buffer chip (MAX232 clone) which connects to it. The COM0 pins also appear to connect to the main I/O ribbon. COM0 is related to TXD0/RXD0 on the V25 via pins 13,14 of JP2 (TX is direct, RX appears to be switched or combined with some other signal via US9, a 74HC08). TXD1/RXD1 connect via 15,16 of JP2 and don't appear to be used on the controller.
There is a CR2016 coin cell. This may provide power for the Rtc and / or battery backed RAM. The daughter board on a Northackton clock was unplugged for at least couple of weeks, separating RAM and Rtc from the battery, but stil appeared to work normally.
There is a 24LC256 EEPROM.
An LDR and an LED are connected to the controller and mounted in the front panel. LED for status or power, LDR to auto-adjust brightness ?
Daughterboard
There is a DIP switch on the daughterboard : on the Northackton clock all switches are set off except bit 1 on one of the boards. This might be setting an RS485 address.
Setting DIP switch 8 ON before the power is applied puts the clock into a test mode. Various patterns are displayed on the screen and the lamp brightness is varied.
Other components are :
- NEC D70320GJ-8 V25 microcontroller
- ST 27C1001-10 1Mbit (128kbyte) EPROM
- Toshiba TC554001AF-70 512kbyte x 8 SRAM
- OKI 62X42B real-time clock with internal crystal
- Linear Technology LTC1235 supervisor (ram protection, reset) circuit
- 74HC138, 74HC32, 74HC04 - probably bus decode
- LK1 - labelled 'w/dog' so presumably enables watchdog in supervisor ic
- LK2 - selects 128k - probably EPROM size option, could take a 27C4001
The daughterboard has an identical number of pins on each edge and can be fitted either way around. The correct orientation is with the DIP switch close to the 2 PIC chips and the SRAM chip close to the coin cell.
Firmware
The daughterboard EPROM contents have been read - available as binary file.
People at LHS has started disassembling the firmware
The PICs have not been read (not tried, don't know if they have security fuses set).
LCD buffer
A ribbon cable runs from the controller to two buffer boards, chained from one to the other via connectors on the buffer boards marked INPUT and OUTPUT. Each buffer board also has two connectors marked GLASS 0 and GLASS 1 which run to the LCD panels. The first buffer board connects to one edge of each of the LCD panels. The second buffer board connects to the opposite edge, again of both panels. So it appears that the total LCD area is divided into 4 for connection purposes.
The signals from the buffer boards to the LCD are not LCD multiplex signals. There are 6 pins with supply voltages (typical of LCD multiplex voltage levels - they vary from about 0 to 6 volts) and 5 pins with digital signals, one of which is a continuously running square wave that probably drives the LCD phase clock. The remaining digital signals only change when the display changes (ie every second) and appear to be 2 data signals, a clock and a strobe that's fired twice at each display change. One of the data signals is unique to each GLASS connector on the buffer board. All the other signals, including one data signal, are common to both glasses. The signals from the second buffer board appear to be quite separate from the first, but these are not yet fully measured.
A logic analyser trace of the signals on one buffer board (the end of the chain) is available. This can be examined using Saleae's logic analyser software - free download, cross platform.
In this trace, chan 0 shows pin 7 on both glasses chan 1 shows pin 8 on both chan 2 shows pin 9 on both chan 3 shows pin 10 on glass 1 only chan 4 shows pin 11 on both chan 5 shows pin 10 on glass 0 only
There is also constant activity on 2 pins of the 3-pinned white connector, adjacent to the red button. Format unknown, but apparently not async serial.
